functional block diagram rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos (8+4) loading dual 12-bit dac AD7537 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features two 12-bit dacs in one package dac ladder resistance matching: 0.5% space saving skinny dip and surface mount packages 4-quadrant multiplication low gain error (1 lsb max over temperature) byte loading structure fast interface timing applications automatic test equipment programmable filters audio applications synchro applications process control general description the AD7537 contains two 12-bit current output dacs on one monolithic chip. a separate reference input is provided for each dac. the dual dac saves valuable board space, and the monolithic construction ensures excellent thermal tracking. both dacs are guaranteed 12-bit monotonic over the full tem- perature range. the AD7537 has a 2-byte (8 lsbs, 4 msbs) loading structure. it is designed for right-justified data format. the control signals for register loading are a0, a1, cs , wr and upd . data is loaded to the input registers when cs and wr are low. to transfer this data to the dac registers, upd must be taken low with wr . added features on the AD7537 include an asynchronous clr line which is very useful in calibration routines. when this is taken low, all registers are cleared. the double buffering of the data inputs allows simultaneous update of both dacs. also, each dac has a separate agnd line. this increases the device versatility; for instance one dac may be operated with agnd biased while the other is connected in the standard configuration. the AD7537 is manufactured using the linear compatible cmos (lc 2 mos) process. it is speed compatible with most microprocessors and accepts ttl, 74hc and 5 v cmos logic level inputs. product highlights 1. dac to dac matching: since both dacs are fabricated on the same chip, precise matching and tracking is inherent. many applications which are not practical using two discrete dacs are now possible. typical matching: 0.5%. 2. small package size: the AD7537 is packaged in small 24-pin 0.3" dips and in 28-terminal surface mount packages. 3. wide power supply tolerance: the device operates on a +12 v to +15 v v dd , with 10% tolerance on this nominal figure. all specifications are guaranteed over this range.
rev. 0 C2C AD7537Cspecifications (v dd = +12 v to +15 v, 6 10%, v refa = v refb = 10 v; i outa = agnd = 0 v, i outb = agndb = 0 v. all specifications t min to t max unless otherwise noted.) ac performance characteristics these characteristics are included for design guidance only and are not subject to test. (v dd = +12 v to +15 v; v refa = v refb = +10 v; i outa = agnda = 0 v, i outb = agndb = 0 v. output amplifiers are ad644 except where noted.) parameter t a = +25 8 ct a = t min , t max units test conditions/comments output current settling time 1.5 m s max to 0.01% of full-scale range. i out load = 100 w , c ext = 13 pf. dac output measured from falling edge of wr . typical value of settling time is 0.8 m s. digital-to-analog glitch lmpulse 7 nv-s typ measured with v refa = v refb = 0 v. i outa , i outb load = 100 w , c ext = 13 pf. dac registers alternately loaded with all 0s and all 1s. ac feedthrough 4 v refa to i outa C70 C65 db max v refa , v refb = 20 v p-p 10 khz sine wave. v refb to i outb C70 C65 db max dac registers loaded with all 0s. power supply rejection d gain/ d v dd 0.01 0.02 % per % max d v dd = v dd max C v dd min output capacitance c outa 70 70 pf max dac a, dac b loaded with all 0s c outb 70 70 pf max c outa 140 140 pf max dac a, dac b loaded with all 1s c outb 140 140 pf max channel-to-channel isolation v refa to i outb C84 db typ v refa = 20 v p-p 10 khz sine wave, v refb = 0 v. both dacs loaded with all 1s. v refb to i outa C84 db typ v refb = 20 v p-p 10 khz sine wave, v refa = 0 v. both dacs loaded with all 1s. digital crosstalk 7 nv-s typ measured for a code transition of all 0s to all 1s. i outa , i outb load = 100 w , c ext = 13 pf. output noise voltage density 25 nv/ ? hz typ measured between r fba and i outa or r fbb and i outb. (10 hzC100 khz) frequency of measurement is 10 hzC100 khz. total harmonic distortion C82 db typ v in = 6 v rms, 1 khz. both dacs loaded with all 1s. notes 1 temperature range as follows: j, k, l versions: C40 c to +85 c; a, b, c versions: C40 c to +85 c; s, t, u versions: C55 c to +125 c specifications subject to change without notice. 2 sample tested at +25 c to ensure compliance. 3 functional at v dd = 5 v, with degraded specifications. 4 pin 12 (dgnd) on ceramic dips is connected to lid. j, a k, b l, c s t u parameter versions versions versions version version version units test conditions/comments accuracy resolution 12 12 12 12 12 12 bits relative accuracy 1 1/2 1/2 1 1/2 1/2 lsb max differential nonlinearity 1 1 1 1 1 1 lsb max all grades guaranteed mono- tonic over temperature. gain error 6 3 1 6 3 2 lsb max measured using r fba , r fbb . both dac registers loaded with all 1s. gain temperature coefficient 2 ; d gain/ d temperature 5 5 5 5 5 5 ppm/ c max typical value is 1 ppm/ c output leakage current i outa +25 c 10 10 10 10 10 10 na max dac a register loaded t min to t max 150 150 150 250 250 250 na max with all 0s i outb +25 c 10 10 10 10 10 10 na max dac b register loaded t min to t max 150 150 150 250 250 250 na max with all 0s reference input input resistance 999999k w min typical input resistance = 14 k w 20 20 20 20 20 20 k w max v refa , v refb input resistance match 3 3 1 3 3 1 % max typically 0.5% digital inputs v ih (lnput high voltage) 2.4 2.4 2.4 2.4 2.4 2.4 v min v iil (input low voltage) 0.8 0.8 0.8 0.8 0.8 0.8 v max i in (input current) +25 c 1 1 1 1 1 1 m a max v in = v dd t min to t max 10 10 10 10 10 10 m a max c in (lnput capacitance) 2 10 10 10 10 10 10 pf max power supply 3 v dd 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 v min/v max i dd 222222ma max
AD7537 rev. 0 C3C timing characteristics limit at limit at limit at t a = C40 8 ct a = +55 8 c parameter t a = +25 8 c to +85 8 c to +125 8 c units test conditions/comments t 1 15 15 30 ns min address valid to write setup time t 2 15 15 25 ns min address valid to write hold time t 3 60 80 80 ns min data setup time t 4 25 25 25 ns min data hold time t 5 0 0 0 ns min chip select or update to write setup time t 6 0 0 0 ns min chip select or update to write hold time t 7 80 80 100 ns min write pulse width t 8 80 80 100 ns min clear pulse width specifications subject to change without notice. absolute maximum ratings* (t a = +25 c unless otherwise stated) v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +17 v v refa , v refb to agnda, agndb . . . . . . . . . . . . . . . . 25 v v rfba , v rfbb to agnda, agndb . . . . . . . . . . . . . . . . 25 v digital input voltage to dgnd . . . . . . . C0.3 v, v dd +0.3 v i outa , i outb to dgnd . . . . . . . . . . . . . . C0.3 v, v dd +0.3 v agnda, agndb to dgnd . . . . . . . . . C0.3 v, v dd +0.3 v power dissipation (any package) to +75 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mw derates above +75 c . . . . . . . . . . . . . . . . . . . . . 6 mw/ c operating temperature range commercial plastic (j, k, l versions) . . . . C40 c to +85 c industrial hermetic (a, b, c versions) . . . C40 c to +85 c extended hermetic (s, t, u versions) . . C55 c to +125 c storage temperature . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7537 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. figure 1. timing diagram ordering guide 1 temperature relative gain package model 2 range accuracy error option 3 AD7537jn C40 c to +85 c 1 lsb 6 lsb n-24 AD7537kn C40 c to +85 c 1/2 lsb 3 lsb n-24 AD7537ln C40 c to +85 c 1/2 lsb 1 lsb n-24 AD7537jp C40 c to +85 c 1 lsb 6 lsb p-28a AD7537kp C40 c to +85 c 1/2 lsb 3 lsb p-28a AD7537lp C40 c to +85 c 1/2 lsb 1 lsb p-28a AD7537aq C40 c to +85 c 1 lsb 6 lsb q-24 AD7537bq C40 c to +85 c 1/2 lsb 3 lsb q-24 AD7537cq C40 c to +85 c 1/2 lsb 1 lsb q-24 AD7537sq C55 c to +125 c 1 lsb 6 lsb q-24 AD7537tq C55 c to +125 c 1/2 lsb 3 lsb q-24 AD7537uq C55 c to +125 c 1/2 lsb 2 lsb q-24 AD7537se C55 c to +125 c 1 lsb 6 lsb e-28a AD7537te C55 c to +125 c 1/2 lsb 3 lsb e-28a AD7537ue C55 c to +125 c 1/2 lsb 2 lsb e-28a notes 1 analog devices reserves the right to ship ceramic packages (d-24a) in lieu of cerdip packages (q-24). 2 to order mil-std-883, class b processed parts, add/883b to part number. contact your local sales office for military data sheet. 3 e = leadless ceramic chip carrier; n = plastic dip; p = plastic leaded chip carrier; q = cerdip. (v dd = +10.8 v to +16.5 v, v refa = v refb = +10 v; i outa = agnda = 0 v, i outb = agndb = 0 v.)
AD7537 rev. 0 C4C pin function description (dip) pin mnemonic description 1 agnda analog ground for dac a. 2i outa current output terminal of dac a. 3r fba feedback resistor for dac a. 4v refa reference input to dac a. 5 cs chip select input active low. 6C14 db0Cdb7 eight data inputs, db0Cdb7. 12 dgnd digital ground. 15 a0 address line 0. 16 a1 address line 1. 17 clr clear input. active low. clears all registers. 18 wr write input. active low. 19 upd updates dac registers from inputs registers. 20 v dd power supply input. nominally +12 v to +15 v, with 10% tolerance. 21 v refb reference input to dac b. 22 r fbb feedback resistor for dac b. 23 i outb current output terminal of dac b. 24 agndb analog ground for dac b. lccc dip plcc pin configurations circuit information C d/a section the AD7537 contains two identical 12-bit multiplying d/a converters. each dac consists of a highly stable r-2r ladder and 12 n-channel current steering switches. figure 2 shows a simplified d/a circuit for dac a. in the r-2r ladder, binary weighted currents are steered between i outa and agnda. the current flowing in each ladder leg is constant, irrespective of switch state. the feedback resistor r fba is used with an op amp (see figures 4 and 5) to convert the current flowing in i outa to a voltage output. figure 2. simplified circuit diagram for dac a equivalent circuit analysis figure 3 shows the equivalent circuit for one of the d/a con- verters (dac a) in the AD7537. a similar equivalent circuit can be drawn for dac b. c out is the output capacitance due to the n-channel switches and varies from about 50 pf to 150 pf with digital input code. the current source i lkg is composed of surface and junction leakages and approximately doubles every 10 c. r 0 is the equivalent output resistance of the device which varies with input code. digital circuit information the digital inputs are designed to be both ttl and 5 v cmos compatible. all logic inputs are static protected mos gates with typical input currents of less than 1 na. table i. AD7537 truth table clr upd cs wr a1 a0 function 1 1 1 x x x no data transfer 1 1 x 1 x x no data transfer 0 x x x x x all registers cleared 1 1 0 0 0 0 dac a ls input register loaded with db7Cdb0 (lsb) 1 1 0 0 0 1 dac a ms input register loaded with db3 (msb)Cdb0 1 1 0 0 1 0 dac b ls input register loaded with db7Cdb0 (lsb) 1 1 0 0 1 1 dac b ms input register loaded with db3 (msb)Cdb0 1 0 1 0 x x dac a, dac b registers updated simultaneously from input registers 1 0 0 0 x x dac a, dac b registers are transparent notes: x = dont care figure 3. equivalent analog circuit for dac a
AD7537 rev. 0 C5C unipolar binary operation (2-quadrant multiplication) figure 4 shows the circuit diagram for unipolar binary opera- tion. with an ac input, the circuit performs 2-quadrant multipli- cation. the code table for figure 4 is given in table ii. operational amplifiers a1 and a2 can be in a single package (ad644, ad712) or separate packages (ad544, ad711, ad op27). capacitors c1 and c2 provide phase compensation to help prevent overshoot and ringing when high-speed op amps are used. for zero offset adjustment, the appropriate dac register is loaded with all 0s and amplifier offset adjusted so that v outa or v outb is 0 v. full-scale trimming is accomplished by loading the dac register with all 1s and adjusting r1 (r3) so that v outa (v outb ) = Cv in (4095/4096). for high temperature op- eration, resistors and potentiometers should have a low tem- perature coefficient. in many applications, because of the excellent gain t.c. and gain error specifications of the AD7537, gain error trimming is not necessary. in fixed refer- ence applications, full scale can also be adjusted by omitting r1, r2, r3, r4 and trimming the reference voltage magnitude. figure 4. AD7537 unipolar binary operation table ii. unipolar binary code table for circuit of figure 4 binary number in dac register analog output, msb lsb v outa or v outb 1111 1111 1111 - v in 4095 4096 ? ? ? ? 1000 0000 0000 - v in 2048 4096 ? ? ? ? =- 1 2 v in 0000 0000 0001 - v in 1 4096 ? ? ? ? 0000 0000 0000 0 v bipolar operation (4-quadrant multiplication) the recommended circuit diagram for bipolar operation is shown in figure 5. offset binary coding is used. with the appropriate dac register loaded to 1000 0000 0000, adjust r1 (r3) so that v outa (v outb ) = 0 v. alternatively, r1, r2 (r3, r4) may be omitted and the ratios of r6, r7 (r9, 10) varied for v outa (v outb ) = 0 v. full-scale trimming can be ac- complished by adjusting the amplitude of v in or by varying the value of r5 (r8). if r1, r2 (r3, r4) are not used, then resistors r5, r6, r7 (r8, r9, r10) should be ratio matched to 0.01% to ensure gain error performance to the data sheet specification. when operating over a wide temperature range, it is important that the resistors be of the same type so that their temperature coefficients match. the code table for figure 5 is given in table iii. figure 5. bipolar operation (offset binary coding) table iii. bipolar code table for offset binary circuit of figure 5 binary number in dac register analog output, msb lsb v outa or v outb 1111 1111 1111 + v in 2047 2048 ? ? ? ? 1000 0000 0001 + v in 1 2048 ? ? ? ? 1000 0000 0000 0 v 0111 1111 1111 - v in 1 2048 ? ? ? ? 0000 0000 0000 - v in 2048 2048 ? ? ? ? =- v in applicationsC
AD7537 rev. 0 C6C separate agnd pins the dacs in the AD7537 have separate agnd lines taken to pins agnda and agndb on the package. this increases the applications versatility of the part. figure 6 is an example of this. dac a is connected in standard fashion as a program- mable attenuator. agnda is at ground potential. dac b is op- erating with agnd b biased to +5 v by the ad584. this gives an output range of +5 v to +10 v. figure 6. AD7537 dacs used in different modes programmable oscillator figure 7 shows a conventional state variable oscillator in which the AD7537 controls the programmable integrators. the fre- quency of oscillation is given by: f = 1 2 p r 6 r 5 1 c 1 c 2 r eq 1 r eq 2 where r eq1 and r eq2 are the equivalent resistances of the dacs. the same digital code is loaded into both dacs. if c1 = c2 and r5 = r6, the expression reduces to f = 1 2 p 1 c 1 r eq 1 r eq 2 since r eq = 2 n r lad n , (r lad = dac ladder resistance). f = 1 2 p 1 c ( n /2 n ) 2 r lad 1 r lad 2 = 1 2 p d c 1 r lad 1 r lad 2 d = n 2 n ? ? ? ? = 1 2 p d c r lad m where m is the dac ladder resistance mismatch ratio, typically 1.005. with the values shown in figure 7, the output frequency varies from 0 hz to 1.38 khz. the amplitude of the output signal at the a3 output is 10 v peak-to-peak and is constant over the entire frequency span. figure 7. programmable state variable oscillator
AD7537 rev. 0 C7C application hints output offset: cmos d/a converters in circuits such as fig- ures 4 and 5 exhibit a code dependent output resistance which in turn can cause a code dependent error voltage at the output of the amplifier. the maximum amplitude of this error, which adds to the d/a converter nonlinearity, depends on v os , where v os is the amplifier input offset voltage. to maintain specified operation, it is recommended that v os be no greater than (25 3 10 C6 ) (v ref ) over the temperature range of operation. suitable op amps are the ad711c and its dual version, the ad712c. these op amps have a wide bandwidth and high slew rate and are recommended for wide bandwidth ac applications. ad711/ad712 settling time to 0.01% is typically 3 m s. temperature coefficients: the gain temperature coefficient of the AD7537 has a maximum value of 5 ppm/ c and typical value of 1 ppm/ c. this corresponds to worst case gain shifts of 2 lsbs and 0.4 lsbs respectively over a 100 c temperature range. when trim resistors r1 (r3) and r2 (r4) are used to ad- just full scale range as in figure 4, the temperature coefficient of r1 (r3) and r2 (r4) should also be taken into account. for further information see gain error and gain temperature co- efficient of cmos multiplying dacs, application note, pub- lication number e630c-5-3/86 available from analog devices. high frequency considerations: AD7537 output capaci- tance works in conjunction with the amplifier feedback resis- tance to add a pole to the open loop response. this can cause ringing or oscillation. stability can be restored by adding a phase compensation capacitor in parallel with the feedback re- sistor. this is shown as c1 and c2 in figures 4 and 5. feedthrough: the dynamic performance of the AD7537 de- pends upon the gain and phase stability of the output amplifier, together with the optimum choice of pc board layout and de- coupling components. a suggested printed circuit layout for figure 4 is shown in figure 8 which minimizes feedthrough from v refa , v refb to the output in multiplying applications. figure 8. suggested layout for AD7537 microprocessor interfacing the byte loading structure of the AD7537 makes it very easy to interface the device to any 8-bit microprocessor system. figures 9 and 10 show two interfaces: one for the mc6809 and the other for the mc68008. figure 11 shows how an AD7537 sys- tem can be easily expanded by tying all the upd lines together and using a single decoder output to control these. this ex- panded system is shown using a z80 microprocessor but it is just as easily configured using any other 8-bit microprocessor system. note how the system shown in figure 11 produces 4 analog outputs with a minimum amount of hardware. figure 9. AD7537Cmc6809 interface figure 10. AD7537Cmc68008 interface figure 11. expanded AD7537 system
AD7537 rev. 0 C8C c978aC5C10/87 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 24-pin plastic dip (n-24) 24-pin cerdip (q-24) 28-terminal leadless ceramic chip carrier (e-28a) 28-terminal plastic leaded chip carrier (p-28a) 24-pin ceramic dip (d-24a)
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